Advanced MOS Device Reliability Characterization

Standards Produced Through NIST Leadership

• EIA/JEDEC JESD35, Procedure for the Wafer-Level Testing of Thin Dielectrics (1996)
• EIA/JEDEC 35-1, General Guidelines for Designing Test Structures (1995)
• EIA/JEDEC 35-2, Test Criteria for the Wafer-Level Testing of Thin Dielectrics (1995)
• ASTM 96F1, Test method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique (1997)
• EIA/JEDEC Pub. No. 128, Guide for Standard Probe Pad Sizes and Layouts for Wafer-Level Electrical Testing
• EIA/JEDEC JESD61, Isothermal test for single-level metal.
• EIA/JEDEC JEP119, SWEAT TEST Standard Procedure
• EIA/JEDEC JESD63, Standard Method for Calculating the Electromigration Model Parameters for Current Density and Temperature.
• ASTM F1260, Constant current density and temperature test for Electromigration
• EIA/JEDEC JEDSD91 Procedure for Characterizing Time-Dependent Dielectric Breakdown of Ultra-Thin Gate Dielectrics

For additional details, please contact John Suehle, Project Leader.

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Date created: 12/7/2005
Last updated: 8/14/2007