Nano-Structures for CD and Interconnect Metrology
Research Activities
This project, in collaboration the NIST Precision Engineering and Statistical Engineering Divisions, has recently designed and implemented a screening experiment to identify which combinations of six pattern-transfer process factors drive down SCCDRM (Single-Crystal CD Reference-Material) reference-feature CDs and their uncertainties. Initial results include CD reductions to 25 nm with superior uniformities.
SCCDRM chip layouts have been designed for three new fabrication ventures featuring 200 mm wafer monolithic implementations. One of these is for a new hybrid optical/e-beam-direct-write process designed to reduce CDs to below 20 nm. Another is to take advantage of an offer by SEMATECH to collaborate on the fabrication of a new generation of SCCDRMs using state-of-the-art 193 nm lithography. The third is to respond to an interest expressed by other NIST operating units to sponsor a joint SRM venture.
Our SCCDRM implementation is well suited to the fabrication of calibrated reference materials for the emerging metrology known as optical-CD (OCD). We have now accomplished the first-ever fabrication and extensive inspection by SEM of gratings suitable for this purpose.
A paper that describes a new simulation program and its use to study the effects of surface and grain-boundary scattering on the effective resistivity of copper in thin planar films and small cross-section lines was completed. The paper was published by the Microelectronics Reliability journal in July 2006.
Project staff completed for publication a new JEDEC standard for electro-migration stress testing with constant current and temperature.
Project staff prepared a comprehensive manuscript on second-generation SCCDRM reference-materials for publication as the lead article in the May-June 2006 issue of the NIST Journal of Research.
As a result of close extended collaboration with the
In close collaboration with the Laboratory for Interconnect and Packaging at the
Work has continued on a new CD metrology based on coplanar waveguide test structures. Extensive e-m field modeling of characteristic impedance and distributed capacitance, which we have conducted in collaboration with the Department of Electrical and Computer Engineering at
A new JEDEC standard, JESD202, was completed and published in March 2006. The standard describes an accelerated stress test method for determining sample estimates and their confidence limits of the median-time-to-failure, sigma, and early percentile of a log-normal distribution, which are used to characterize the electromigration failure-time distribution of equivalent metal lines subjected to a constant current-density and temperature stress. Procedures are provided to analyze complete and singly, right-censored failure-time data.
The computer-aided design (CAD) of a new test chip for the fabrication of test structures that can be electrically calibrated to serve as an overlay reference material for high-density interconnect fabrication has been completed. A program to simulate and validate the calibration of the standard has been applied to the design, and the fabrication of a wafer-lot has been initiated.
In collaboration with NIST operations in
