Chong
Jiang
University:
Gradation Date: May 2008
Hometown:
My Project: Nanocapacitance Measurement
The goal of this project is to investigate methods of measuring sub-picofarad capacitors, with the eventual goal of attofarad resolution. Capacitance is an important characteristic for many novel semiconductor devices – such as nanotube-based field-effect transistors – yet these nanostructures have capacitances that are not readily measurable. We are therefore working towards creating and testing various methods of capacitance measurement. My involvement in this project this summer has consisted of four main components.
The first of these consisted of setting up an off-the-shelf constant-voltage-charging capacitance measurement board from Irvine Sensors. The circuit itself is designed for real-time monitoring of small changes in capacitance (such as in airbag sensors), with an analog output. I adapted this circuit to make slower and more precise measurements (~2fF) of absolute capacitance by using a LabVIEW-based data acquisition and control scheme. Unresolved issues include the inability to apply a bias voltage, the long time required for averaging, and the presence of drift.
The second component I worked on was finding alternative approaches for capacitance measurement. One such approach is to replace the constant-voltage source with a constant-current source, with the primary advantages being the elimination of large transient currents at the start of the charging process. A prototype circuit for this method has been designed, and is in the process of being created.
The third component was the investigation of an RC time-constant approach. The application of a voltage step function to the series connection of a capacitor and a resistor results in an exponential decay of voltage at the intermediate node versus time. By sampling this voltage at high sampling rates (~1GS/s), averaging, and fitting the resultant waveform to an exponential curve, we can extract the time-constant τ = RC. Dividing by the measured resistor value then yields C. In actual operation, the one capacitor C is replaced by a parallel combination of a small capacitor and the very small capacitor under test (DUT). This changes the problem into a differential measurement, between τ with the DUT inserted, and τ without the DUT. Preliminary data shows that this method scales well from pF to fF, while sub-fF resolution would require prohibitively long averaging times.
The final, and largest, component of my work this summer involved the measurement of a series of chips, each with several hundred capacitors, with designed capacitances ranging from 0.4fF to 1pF. Using an HP4284A LCR meter and a Cascade semi-automated probe station, we obtained capacitance vs. voltage (C-V) curves for metal-oxide-semiconductor (MOS) and metal-insulator-metal (MIM) capacitors on five of the chips. We were then able to examine the fit between measured and theoretical values (residuals bounded by ~4fF after a linear fit), as well as determine the resolution of our measurements for the same capacitor across days (~0.1fF), identical capacitors on the same chip (~0.4fF), and identical capacitors between chips (~???). This not only confirmed the design of these chips, but also yields a benchmark for which future work in very small capacitance measurement can be compared with.
